During the production of silicon slices, silicon plates or wafers for the semiconductor and solar cell industry, the wafers are subjected to a range of mechanical and/or chemical treatment steps in order to impart the desired sizes and product properties to them. The text which follows describes the process steps for producing solar cells which are customary according to the prior art.
First of all, a silicon ingot is cut into slices, also known as wafers, using a wire saw. After they have been cut, the wafers are cleaned in order to remove what is known as a sawing slurry. This is generally followed by a wet-chemical saw damage etch using suitable chemicals, such as in particular lyes, in order to remove the defect-rich layer which results from the cutting process. The wafers are then washed and dried.
The wafers or substrates are generally monocrystalline or polycrystalline silicon waters which are p-doped with boron. To produce a p n junction required for the solar cell to function, one side of the silicon wafers is n-doped. This n-doping is usually carried out by means of phosphorus doping. In the process, the substrate or silicon surface is modified by the incorporation of phosphorus atoms, the phosphorus source used generally being a gas or a liquid-pasty composition. After suitable incubation or coating of the silicon wafers in the gas or with the composition, the phosphorus atoms diffuse into, accumulate on or are incorporated into the silicon surface by heating to usually 800 to 1000° C. After this phosphorus doping, the silicon plate has a layer which is up to a few μm thick and is n+-doped with phosphorus.
One problem with this surface modification is that generally not only the desired surface (top side) but also the opposite surface (underside) and in particular the peripheral edges of the substrate waters are modified or doped by the treatment, which in subsequent use leads to the risk of short circuits, since the edges are electrically conductive. Additional doping of the underside, as is effected for example by vapor phase doping, however, is in many cases acceptable, since the n+ doping of the undersides or back surfaces of the plates is then generally converted into a p doping, as is required, for example, for the subsequent contact-connection of a solar cell, by the formation of an “aluminum back surface field”. However, wafers which have been treated in this manner always have edges which include phosphorus atoms and are therefore electrically conductive, which without further treatment leads to silicon wafers having the abovementioned drawback of a risk of short circuits forming in subsequent use.
The prior art has developed various processes for eliminating this problem. By way of example, the problem of the electrically conductive edges is solved by the edges being ground away mechanically. However, the grinding, like the sawing, can produce detects in the crystal structure, leading to electrical losses. However, the main drawback of this procedure consists in the considerable risk of the sensitive wafers breaking.
Furthermore, it is proposed that the conductive layer which is present on the underside or back surface be interrupted in the outer region or at the edge by the action of a laser beam. However, this edge isolation by means of a laser is not yet an established process and throws up problems in particular with regard to the automation of the process and the throughput which can be achieved. Furthermore, there is a risk that subsequent process steps and the efficiency of, for example, a correspondingly produced cell may be adversely affected by accumulation of combustion products formed during the laser treatment on the wafer surface.
Finally, it is proposed that a plurality of plates be stocked and the edges of the plate stock be etched by means of plasma. The edge isolation by means of plasma requires the wafers to be stacked on top of one another. Both the stacking and the handling of the stacks take place either manually or in automated fashion, which involves a very high level of outlay on equipment. Consequently, processing in stacks always involves interrupting or reorganizing the production flow, specifically both in the context of batch production, in which the wafers are transported in process carriers, and in the case of inline production, in which the wafers are passed through the various process steps on conveyor belts or rolls, etc. Furthermore, the complex handling means that the wafers are once again exposed to an increased risk of breaking.
Another process in which only the edges are treated is proposed in DE 100 32 279 A1. DE 100 32 279 A1 describes a process for the chemical passivation of edge defects in silicon solar cells by etching out the edge defects. For this purpose, an etchant is applied to the edges of the silicon solar cells using a felt cloth impregnated with etchant.
Further processes which are known from the prior art solve the problem of the electrically conductive edges by removing the conductive layer on the edges and one side of the substrate by means of etching in an acid bath. By way of example, DE 43 24 647 A1 and US 2001/0029978 A1 describe a multistage etching process in which a substrate is completely immersed in an acid bath. Since it is only the back surface and the edges of the substrate which are being etched here in each case, the front surface of the substrate has to be protected by an acid-resistant photoresist or a mask.
In particular, the etching process described in DE 43 24 647 A1 and US 2001/0029978 A1 is not just time-consuming, since special working steps are required for the application and removal of protective layers, but also requires the use of additional materials. In particular, the application and removal of protective layers entails the risk of the substrates which are to be treated being adversely affected. Should a protective layer applied be defective or damaged, there is a risk of the front surfaces of the substrates being damaged during etching, so that the substrates become unusable.
Therefore, all these processes which have been described in the prior art serve to decouple the two surfaces (top side and underside) in terms of their electrical conductivity, but they involve the in some cases serious problems of the type described above.